core0_dbg_rst=core0_dbg_rst_0, core0_rst=core0_rst_0, lockup_rst=lockup_rst_0, dbg_rst_msk_pg=dbg_rst_msk_pg_0
SRC Control Register
| lockup_rst | lockup reset enable bit 0 (lockup_rst_0): disabled 1 (lockup_rst_1): enabled |
| mask_wdog_rst | Mask wdog_rst_b source 5 (mask_wdog_rst_5): wdog_rst_b is masked 10 (mask_wdog_rst_10): wdog_rst_b is not masked (default) |
| core0_rst | Software reset for core0 only 0 (core0_rst_0): do not assert core0 reset 1 (core0_rst_1): assert core0 reset |
| core0_dbg_rst | Software reset for core0 debug only 0 (core0_dbg_rst_0): do not assert core0 debug reset 1 (core0_dbg_rst_1): assert core0 debug reset |
| dbg_rst_msk_pg | Do not assert debug resets after power gating event of core 0 (dbg_rst_msk_pg_0): do not mask core debug resets (debug resets will be asserted after power gating event) 1 (dbg_rst_msk_pg_1): mask core debug resets (debug resets won’t be asserted after power gating event) |
| mask_wdog3_rst | Mask wdog3_rst_b source 5 (mask_wdog3_rst_5): wdog3_rst_b is masked 10 (mask_wdog3_rst_10): wdog3_rst_b is not masked |